User2User Mid-Atlantic 2026

Presented by Siemens:
Signal and Power Integrity (SI/PI) experts are often the bottleneck in the design cycle, receiving layouts that contain "gross anomalies" which should have been caught weeks earlier. This session introduces the "Big Rock" methodology—a push-button automation strategy designed to make design tools analysis-aware. We will demonstrate how automated S-parameter extraction, Time Domain Simulation, and PI design checks can be moved into the hands of the broader design team. By identifying pesky anomalies early, SI/PI engineers can focus their expertise on final sign-off and complex problem-solving rather than basic design iterations.

Presented by Siemens:
Documentation is a critical step in the PCB design process, yet it is often a manual, error-prone bottleneck that can consume 20% or more of the total design cycle. This seminar provides a comprehensive introduction to Siemens BluePrint-PCB, the industry standard for automated PCB documentation.

We will explore how BluePrint-PCB replaces traditional, labor-intensive CAD methods with intelligent, data-driven automation. By leveraging drag-and-drop generation for assembly drawings, drill charts, and parts lists, BluePrint-PCB ensures synchronization between the source design and the final documentation. Attendees will learn how this transition can reduce documentation time by, eliminate manual drawing errors, and significantly improve first-pass manufacturing readiness. Whether you are a designer looking to spend more time on engineering and less on drawings, or a lead aiming to shorten time-to-market, this session will demonstrate how to transform your manufacturing handoff into a seamless, high-efficiency process.

Presented by: Siemens
As PCB designs become increasingly complex, ensuring all electrical, physical, and manufacturing requirements are met is essential for achieving reliable, high-quality designs. Manual design reviews can be time-consuming and may allow issues to go undetected until late in the development process, when corrections are more costly. This presentation focuses on electrical checks that can uncover potential EMI/SI/PI issues prior to running full board-level simulations to streamline the review process. Discussion will include recommended methodologies for setting up and executing ERCs, interpreting violations, and improving collaboration between PCB design and engineering teams. Join us to learn how automated design reviews with HyperLynx can reduce risk, minimize re-spins, and help move your designs from risky to ready.

Presented by: JHU APL
Static & formal verification for RTL and FPGA teams. A practical introduction to the portfolio, analysis flow, result semantics, debug, and deployment.

Presented by: Siemens
As modern PCB designs push the boundaries of high-performance computing, the requirements for robust Power Distribution Network (PDN) design and thermal management have become increasingly complex. Failure to address these challenges can lead to catastrophic board damage, logic errors, or long-term reliability issues. This presentation explores a comprehensive, multi-domain approach to PDN verification and optimization using the Siemens EDA toolset.

Through a detailed case study centered on the AMD Versal™ platform, we demonstrate a unified workflow covering DC, thermal, and AC performance:

• DC Analysis: Utilizing HyperLynx DC Drop to analyze IR drop, current density, and point-to-point resistance, ensuring adequate power delivery while identifying potential "hot spots" or excessive current densities that threaten board integrity.
• Thermal Management: Leveraging Simcenter Flotherm to validate junction temperatures and develop precise simulation-driven constraints, preventing overheating and ensuring long-term system reliability.
• AC Optimization: Applying HyperLynx AC Decoupling analysis to optimize capacitor selection and placement, effectively minimizing voltage ripple and ensuring stable current delivery to fast-switching ICs.

Presented by: Siemens
With HyperLynx AMS, SPICE simulations can be integrated into your Xpedition Designer schematic, where one schematic drives your simulation results and PCB layout. Not only can you verify that your circuitry works properly after schematic creation, you can utilize the integration of HyperLynx AMS and Xpedition to include the parasitic effects of your PCB layout in your SPICE simulation.

During this presentation, learn how to setup your PCB schematic for SPICE simulation using HyperLynx AMS. Easily sweep parameters to improve your circuit’s performance and use Monte-Carlo analysis to confirm that your design will work across your parts tolerances. After schematic verification, extract parasitic effects from your layout to include these effects in your simulation, getting accurate results that reflect a manufactured circuits performance.

Presented by: Siemens
As modern SoC design cycles accelerate, early software bring-up and system-level validation are becoming critical bottlenecks in the verification flow. This presentation explores Avery Software-Aware VIP (SAV), a software-aware verification approach that integrates QEMU and Arm Fast Models with virtualized SoC environments to deliver realistic software stimulus before silicon availability.

We will walk through several supported platforms, including Arm-based CSS, RISC-V, and Xilinx Adaptive SoCs, and examine the debugging capabilities of SAV for analyzing software-hardware interactions, including protocol and system-level visibility.

We will also look at how SAV is designed to integrate seamlessly into AI-enabled verification flows, enabling richer software-driven stimulus, faster debug, and more efficient system-level validation.