User2User Mid-Atlantic 2026

Presented by: Siemens
AI is a five-layer architecture spanning energy, chips, infrastructure, models and applications, and Siemens spans these layers across more than 30 industries. But powering intelligence at scale demands one thing above all else: chips. And chips depend on EDA.

Semiconductor design today faces a perfect storm of challenges: designs of unprecedented complexity rooted in advanced packaging, heterogeneous integration and hardware-software convergence; a talent crisis with the industry on track to need over one million additional skilled workers globally by 2030; and surging demand fueled by AI infrastructure build-out. This is the frontier of AI-native EDA and the focus of this presentation.

Siemens' response is a clear, three-pillar AI strategy built around speed, productivity and confidence. Faster engines harness GPU acceleration, in-tool machine learning and reinforcement learning to dramatically reduce simulation and verification runtimes across the full design cycle, delivering speed improvements of up to 1000x. Smarter execution deploys purpose-built agentic AI that autonomously orchestrates multi-tool workflows from high-level synthesis through physical verification and board design, delivering productivity gains of 10 to 50x. Trusted outcomes continuously validate every agent decision against our physics-based EDA engines, creating self-verifying AI workflows that increase confidence through trusted engineering outcomes.

EDA designs the chips that power AI. Without it, the entire stack stalls. This presentation explores how AI-native EDA, built on faster engines, smarter execution and trusted outcomes, makes sure it never does.

Presented by: Northrop Grumman and Siemens
This paper will report on the lessons learned during the integration of Supplychain which imports Supplyframe data into a common corporate EDM Library Server. It will provide a roadmap for those who are considering migrating Supplyframe/Supplychain into EDM Library.
Supplyframe introduces a new catalog structure and characteristics to the EDM library. This paper will provide useful instructions to migrate an existing EDM Library to the new structure.

In addition, I will discuss the useful items that Supplyframe adds to engineer’s toolbox to implement a Design for Sourcing process at the beginning of a project. This will enable engineers to quickly identify possible problems with their BOM before final review.

Presented by Siemens:
Signal and Power Integrity (SI/PI) experts are often the bottleneck in the design cycle, receiving layouts that contain "gross anomalies" which should have been caught weeks earlier. This session introduces the "Big Rock" methodology—a push-button automation strategy designed to make design tools analysis-aware. We will demonstrate how automated S-parameter extraction, Time Domain Simulation, and PI design checks can be moved into the hands of the broader design team. By identifying pesky anomalies early, SI/PI engineers can focus their expertise on final sign-off and complex problem-solving rather than basic design iterations.

Presented by Siemens:
Documentation is a critical step in the PCB design process, yet it is often a manual, error-prone bottleneck that can consume 20% or more of the total design cycle. This seminar provides a comprehensive introduction to Siemens BluePrint-PCB, the industry standard for automated PCB documentation.

We will explore how BluePrint-PCB replaces traditional, labor-intensive CAD methods with intelligent, data-driven automation. By leveraging drag-and-drop generation for assembly drawings, drill charts, and parts lists, BluePrint-PCB ensures synchronization between the source design and the final documentation. Attendees will learn how this transition can reduce documentation time by, eliminate manual drawing errors, and significantly improve first-pass manufacturing readiness. Whether you are a designer looking to spend more time on engineering and less on drawings, or a lead aiming to shorten time-to-market, this session will demonstrate how to transform your manufacturing handoff into a seamless, high-efficiency process.

Presented by: Reliable MicroSystems
Vertically Integrated Radiation-Aware Design (VIRAD) integrates radiation effects modeling directly into IC design workflows, enabling early identification of terrestrial neutron and space environment vulnerabilities. Using technology-specific RDKs environment-based REMs, and user schematic/layout files, VIRAD rapidly determines critical charge, sensitive nodes, and layout dependent failure cross-sections. Its schematic and layout analysis engines provide fast and accurate predictions for neutron, heavy-ion, and total dose environments, reducing dependence on limited test facilities and costly design re-spins. VIRAD supports pre-test configuration planning and comparison with measured data, offering an efficient pathway for radiation-aware design in advanced semiconductor technologies.

VIRAD combines EDA integration, technology information, technology radiation response, and users’ design schematic/layout files to determine the radiation-induced failure mechanisms present in a cell. The software features a modular approach to EDA integration, radiation dependencies, including Radiation Development Kits (RDKs) which contain pertinent technology information for radiation effects, and Radiation Environment Modules (REMs) which contain specific models and algorithms for determining radiation response in a particular environment. Users work with an RDK, that sits alongside the EDA tool flows and he foundry’s PDK, for all of their designs in a particular technology. REMs allow users to evaluate their circuit’s performance in the environments of interest.

VIRAD leverages critical design information from Calibre to enable the layout-aware analysis. VIRAD will be integrating with the full custom flow, including S-Edit and L-Edit, Solid, and Calibre PERC. This talk will discuss the capabilities of VIRAD, integration with Calibre, and the roadmap for continued Custom IC flow integration.

Presented by: L3Harris
As PCB complexity increases and development cycles shrink, designers must adopt modern methodologies to ensure first-pass fabrication success. This presentation explores a comprehensive approach to modern PCB design, focusing on strategies that bridge the gap between conceptual routing and total manufacturing readiness.

We will delve into the practical application of Physical Reuse to streamline workflows and share essential routing "Tips & Tricks" that solve common layout bottlenecks. A key focus will be the integration of RF design through a ""shift-left" approach—moving critical analysis earlier in the design process to guarantee fabrication success. Furthermore, the session will highlight techniques for accelerating high-speed design projects. By leveraging specific formulas and variables, David will demonstrate how to complete complex, high-speed designs in significantly reduced timeframes without compromising signal integrity.

Presented by: Siemens
As PCB designs become increasingly complex, ensuring all electrical, physical, and manufacturing requirements are met is essential for achieving reliable, high-quality designs. Manual design reviews can be time-consuming and may allow issues to go undetected until late in the development process, when corrections are more costly. This presentation focuses on electrical checks that can uncover potential EMI/SI/PI issues prior to running full board-level simulations to streamline the review process. Discussion will include recommended methodologies for setting up and executing ERCs, interpreting violations, and improving collaboration between PCB design and engineering teams. Join us to learn how automated design reviews with HyperLynx can reduce risk, minimize re-spins, and help move your designs from risky to ready.

Presented by: JHU APL
Static & formal verification for RTL and FPGA teams. A practical introduction to the portfolio, analysis flow, result semantics, debug, and deployment.

Presented by: Siemens
Chip design leaves no room for error and no tolerance for delay: tapeout schedules are fixed and silicon costs are high. The industry is moving from autonomous task orchestration toward fully autonomous, long-running workflows that verify themselves at every step, and our Fuse EDA AI Agent is at the center of that shift, continuously validating decisions against our deterministic, physics-based EDA engines. Optimized by NVIDIA AI infrastructure, our agentic workflows improve token efficiency, tool-calling reliability, and time-to-results. Join this session to see the latest autonomous demos across front-end, verification, and physical implementation for both IC and 3D IC design.

Presented by: Siemens
Documentation is a critical step in the PCB design process, yet it is often a manual, error-prone bottleneck that can consume 20% or more of the total design cycle. This seminar provides a comprehensive introduction to Siemens BluePrint-PCB, the industry standard for automated PCB documentation.

We will explore how BluePrint-PCB replaces traditional, labor-intensive CAD methods with intelligent, data-driven automation. By leveraging drag-and-drop generation for assembly drawings, drill charts, and parts lists, BluePrint-PCB ensures synchronization between the source design and the final documentation. Attendees will learn how this transition can reduce documentation time by, eliminate manual drawing errors, and significantly improve first-pass manufacturing readiness. Whether you are a designer looking to spend more time on engineering and less on drawings, or a lead aiming to shorten time-to-market, this session will demonstrate how to transform your manufacturing handoff into a seamless, high-efficiency process.

Presented by: Siemens
As modern PCB designs push the boundaries of high-performance computing, the requirements for robust Power Distribution Network (PDN) design and thermal management have become increasingly complex. Failure to address these challenges can lead to catastrophic board damage, logic errors, or long-term reliability issues. This presentation explores a comprehensive, multi-domain approach to PDN verification and optimization using the Siemens EDA toolset.

Through a detailed case study centered on the AMD Versal™ platform, we demonstrate a unified workflow covering DC, thermal, and AC performance:

• DC Analysis: Utilizing HyperLynx DC Drop to analyze IR drop, current density, and point-to-point resistance, ensuring adequate power delivery while identifying potential "hot spots" or excessive current densities that threaten board integrity.
• Thermal Management: Leveraging Simcenter Flotherm to validate junction temperatures and develop precise simulation-driven constraints, preventing overheating and ensuring long-term system reliability.
• AC Optimization: Applying HyperLynx AC Decoupling analysis to optimize capacitor selection and placement, effectively minimizing voltage ripple and ensuring stable current delivery to fast-switching ICs.

Presented by: Siemens
This session will provide an overview of 3D IC and chiplet technologies as well as their various heterogeneous integration options. It will show the disruptive characteristics of these technologies on design methodology including the impact on system performance.

It will also highlight key considerations for using 3D IC and chiplets including topics like design planning, physical implementation, physical verification, and electrical/thermal performance.

What you’ll learn:

• Why we need chiplets to address issues like the reticle limit
• What design considerations are there for 3D IC Packaging
• How do issues like thermal design differ with 3D IC packages
• Introduction to Siemens solutions for 3D IC and Chiplets

Presented by: Siemens
As PCB designs continue to evolve with high-speed signaling, micro-BGAs, and dense routing, traditional physical test access has become a critical bottleneck. To ensure reliable manufacturing, test planning can no longer be an afterthought; it must be a collaborative process aligned with design realities. This presentation focuses on a solution for optimizing test strategies by leveraging boundary scan and clustering capabilities to validate interconnected nets where physical access is limited. We will delve into 'what-if' scenario analysis to identify the ideal mix of test methods and demonstrate how to use historical quality data – such as DPMO metrics –  to focus coverage on high-impact failure modes. Join us to learn how to streamline your test planning flow and gain knowledge on maximizing coverage before design constraints lock you out.

Presented by: Siemens
With HyperLynx AMS, SPICE simulations can be integrated into your Xpedition Designer schematic, where one schematic drives your simulation results and PCB layout. Not only can you verify that your circuitry works properly after schematic creation, you can utilize the integration of HyperLynx AMS and Xpedition to include the parasitic effects of your PCB layout in your SPICE simulation.

During this presentation, learn how to setup your PCB schematic for SPICE simulation using HyperLynx AMS. Easily sweep parameters to improve your circuit’s performance and use Monte-Carlo analysis to confirm that your design will work across your parts tolerances. After schematic verification, extract parasitic effects from your layout to include these effects in your simulation, getting accurate results that reflect a manufactured circuits performance.

Presented by: Siemens
As modern SoC design cycles accelerate, early software bring-up and system-level validation are becoming critical bottlenecks in the verification flow. This presentation explores Avery Software-Aware VIP (SAV), a software-aware verification approach that integrates QEMU and Arm Fast Models with virtualized SoC environments to deliver realistic software stimulus before silicon availability.

We will walk through several supported platforms, including Arm-based CSS, RISC-V, and Xilinx Adaptive SoCs, and examine the debugging capabilities of SAV for analyzing software-hardware interactions, including protocol and system-level visibility.

We will also look at how SAV is designed to integrate seamlessly into AI-enabled verification flows, enabling richer software-driven stimulus, faster debug, and more efficient system-level validation.

Presented by: JHU APL
This presentation covers three practical uses of automation and AI in ASIC design. First, agentic AI is used to trace scan-chain failures, find the first bad stage, and identify timing problems. Second, a hybrid Aprisa, Custom Layout tools, and Calibre flow supports custom routing while keeping implementation and signoff controlled. Third, pad-ring creation is automated from a structured pad list, generating both RTL and physical placement data. Together, these methods reduce manual effort, improve consistency, and make complex design flows easier to repeat, review, debug, and verify.