User2User Mid-Atlantic 2026

Presented by: Northrop Grumman and Siemens
This paper will report on the lessons learned during the integration of Supplychain which imports Supplyframe data into a common corporate EDM Library Server. It will provide a roadmap for those who are considering migrating Supplyframe/Supplychain into EDM Library.
Supplyframe introduces a new catalog structure and characteristics to the EDM library. This paper will provide useful instructions to migrate an existing EDM Library to the new structure.

In addition, I will discuss the useful items that Supplyframe adds to engineer’s toolbox to implement a Design for Sourcing process at the beginning of a project. This will enable engineers to quickly identify possible problems with their BOM before final review.

Presented by Siemens:
Documentation is a critical step in the PCB design process, yet it is often a manual, error-prone bottleneck that can consume 20% or more of the total design cycle. This seminar provides a comprehensive introduction to Siemens BluePrint-PCB, the industry standard for automated PCB documentation.

We will explore how BluePrint-PCB replaces traditional, labor-intensive CAD methods with intelligent, data-driven automation. By leveraging drag-and-drop generation for assembly drawings, drill charts, and parts lists, BluePrint-PCB ensures synchronization between the source design and the final documentation. Attendees will learn how this transition can reduce documentation time by, eliminate manual drawing errors, and significantly improve first-pass manufacturing readiness. Whether you are a designer looking to spend more time on engineering and less on drawings, or a lead aiming to shorten time-to-market, this session will demonstrate how to transform your manufacturing handoff into a seamless, high-efficiency process.

Presented by: L3Harris
As PCB complexity increases and development cycles shrink, designers must adopt modern methodologies to ensure first-pass fabrication success. This presentation explores a comprehensive approach to modern PCB design, focusing on strategies that bridge the gap between conceptual routing and total manufacturing readiness.

We will delve into the practical application of Physical Reuse to streamline workflows and share essential routing "Tips & Tricks" that solve common layout bottlenecks. A key focus will be the integration of RF design through a ""shift-left" approach—moving critical analysis earlier in the design process to guarantee fabrication success. Furthermore, the session will highlight techniques for accelerating high-speed design projects. By leveraging specific formulas and variables, David will demonstrate how to complete complex, high-speed designs in significantly reduced timeframes without compromising signal integrity.

Presented by: JHU APL
Static & formal verification for RTL and FPGA teams. A practical introduction to the portfolio, analysis flow, result semantics, debug, and deployment.

Presented by: Siemens
Documentation is a critical step in the PCB design process, yet it is often a manual, error-prone bottleneck that can consume 20% or more of the total design cycle. This seminar provides a comprehensive introduction to Siemens BluePrint-PCB, the industry standard for automated PCB documentation.

We will explore how BluePrint-PCB replaces traditional, labor-intensive CAD methods with intelligent, data-driven automation. By leveraging drag-and-drop generation for assembly drawings, drill charts, and parts lists, BluePrint-PCB ensures synchronization between the source design and the final documentation. Attendees will learn how this transition can reduce documentation time by, eliminate manual drawing errors, and significantly improve first-pass manufacturing readiness. Whether you are a designer looking to spend more time on engineering and less on drawings, or a lead aiming to shorten time-to-market, this session will demonstrate how to transform your manufacturing handoff into a seamless, high-efficiency process.

Presented by: Siemens
As PCB designs continue to evolve with high-speed signaling, micro-BGAs, and dense routing, traditional physical test access has become a critical bottleneck. To ensure reliable manufacturing, test planning can no longer be an afterthought; it must be a collaborative process aligned with design realities. This presentation focuses on a solution for optimizing test strategies by leveraging boundary scan and clustering capabilities to validate interconnected nets where physical access is limited. We will delve into 'what-if' scenario analysis to identify the ideal mix of test methods and demonstrate how to use historical quality data – such as DPMO metrics –  to focus coverage on high-impact failure modes. Join us to learn how to streamline your test planning flow and gain knowledge on maximizing coverage before design constraints lock you out.

Presented by: Siemens
As modern SoC design cycles accelerate, early software bring-up and system-level validation are becoming critical bottlenecks in the verification flow. This presentation explores Avery Software-Aware VIP (SAV), a software-aware verification approach that integrates QEMU and Arm Fast Models with virtualized SoC environments to deliver realistic software stimulus before silicon availability.

We will walk through several supported platforms, including Arm-based CSS, RISC-V, and Xilinx Adaptive SoCs, and examine the debugging capabilities of SAV for analyzing software-hardware interactions, including protocol and system-level visibility.

We will also look at how SAV is designed to integrate seamlessly into AI-enabled verification flows, enabling richer software-driven stimulus, faster debug, and more efficient system-level validation.