User2User Mid-Atlantic 2026

Agenda

Filter by Track

Show all ASIC & FPGA: advanced functional verification (4) New technologies in Custom ASIC Design, 3D IC and AI (4) PCB design and design for manufacturing (4) PCB simulation (4)

10:00 AM

ASIC & FPGA: The AI-driven verification revolution: from embedded intelligence to agentic sign-off

Presented by Siemens:
Documentation is a critical step in the PCB design process, yet it is often a manual, error-prone bottleneck that can consume 20% or more of the total design cycle. This seminar provides a comprehensive introduction to Siemens BluePrint-PCB, the industry standard for automated PCB documentation.

We will explore how BluePrint-PCB replaces traditional, labor-intensive CAD methods with intelligent, data-driven automation. By leveraging drag-and-drop generation for assembly drawings, drill charts, and parts lists, BluePrint-PCB ensures synchronization between the source design and the final documentation. Attendees will learn how this transition can reduce documentation time by, eliminate manual drawing errors, and significantly improve first-pass manufacturing readiness. Whether you are a designer looking to spend more time on engineering and less on drawings, or a lead aiming to shorten time-to-market, this session will demonstrate how to transform your manufacturing handoff into a seamless, high-efficiency process.

Moses Satyasekaran

11:10 AM

ASIC & FPGA: Questa One static formal verification

Presented by: JHU APL
Static & formal verification for RTL and FPGA teams. A practical introduction to the portfolio, analysis flow, result semantics, debug, and deployment.

Karu Karunakaran

01:00 PM

Session information coming soon

02:00 PM

ASIC & FPGA: Questa One software-aware verification IP: Simplifying HW/SW co-simulation for faster, more reliable SoC validation

Presented by: Siemens
As modern SoC design cycles accelerate, early software bring-up and system-level validation are becoming critical bottlenecks in the verification flow. This presentation explores Avery Software-Aware VIP (SAV), a software-aware verification approach that integrates QEMU and Arm Fast Models with virtualized SoC environments to deliver realistic software stimulus before silicon availability.

We will walk through several supported platforms, including Arm-based CSS, RISC-V, and Xilinx Adaptive SoCs, and examine the debugging capabilities of SAV for analyzing software-hardware interactions, including protocol and system-level visibility.

We will also look at how SAV is designed to integrate seamlessly into AI-enabled verification flows, enabling richer software-driven stimulus, faster debug, and more efficient system-level validation.

Alaa Abdelmoaty