Logo - Siemens EDA Forum PCB & FPGA Design 2026 - Mölndal
Servicenavigation
08:30 AM
Registration
09:00 AM
Welcome
09:15 AM
Siemens Keynote AI update and Fuse Open
10:00 AM
Model-based systems engineering update
10:30 AM
Break - Transition to Parallel Sessions
10:45 AM
EDM in the Cloud - What´s New in EDM
Xpedition EDM Cloud Server extends Siemens' proven Enterprise Data Management platform through a Siemens-managed cloud deployment model designed to reduce IT burden, accelerate implementation, and simplify ongoing maintenance. Learn how organizations can improve data governance, collaboration, and design productivity while leveraging enterprise-grade cloud infrastructure and best-practice deployment templates.
Track
PCB systems design
What's New in Questa One for FPGA Verification
Explore the latest Questa One capabilities for FPGA simulation and debug, including improved VHDL support, faster simulation and advanced debugging. See how these enhancements can help engineering teams find problems earlier and shorten verification cycles.
Track
FPGA verification
12:00 PM
Lunch
01:00 PM
Where Better PCB Design Begins - What´s New in HyperLynx
Front-end design constraint planning is the first step toward analysis-driven PCB design. By shifting constraint definition and validation earlier in the process, teams can improve predictability, catch issues sooner, and avoid costly late-stage iterations. Siemens EDA PCB analysis tools enable this shift-left approach in the front-end phase, helping lay the foundation for more efficient, reliable, and optimized PCB development.
Track
PCB systems design
Taking VHDL Verification Beyond Directed Testing
Discover practical ways to move beyond hand-written directed tests using reusable verification components, constrained-random testing and functional coverage. This session will show how VHDL teams can improve test quality and uncover corner-case bugs without having to replace their existing methodology.
Track
FPGA verification
01:45 PM
Invent the future, dont inspect the past
This session starts with an introduction to HyperLynx DRC, covering its role in PCB design verification and how analysis-driven rule checking helps identify design issues early in the development process. Building on this foundation, attendees will learn a practical workflow for creating HyperLynx DRC custom rule checks with AI support. The session demonstrates how complex verification concepts can be transformed into executable checks, enabling faster validation.
Track
PCB systems design
Bringing FPGA Verification into Continuous Integration
Learn how to integrate FPGA simulation and regression testing into automated development workflows using Git, Jenkins and other continuous integration platforms. See how automation can provide faster feedback, improve repeatability and prevent problems from reaching later stages of development.
Track
FPGA verification
02:30 PM
Break
03:00 PM
Maximum Efficiency in PCB Design: BluePrint & TestWay Expand the Valor DFM Product Family - What´s New in Valor
Are you struggling with the complexities of modern PCB designs, which often lead to unexpected challenges in manufacturing and testing? Discover how the expansion of the Siemens EDA Valor DFM product family with the integration of BluePrint (DownStream) and TestWay (Aster) is revolutionizing your design process. These powerful new additions enable rapid and comprehensive optimization: BluePrint streamlines the creation of accurate manufacturing documentation, while TestWay efficiently analyzes and optimizes test coverage. By proactively addressing manufacturing and testability, you minimize costly design revisions, accelerate time to market, and ensure superior product quality and reliability. See how this comprehensive solution transforms your New Product Introduction (NPI) process for more efficient, predictable, and ultimately successful product development. - Add more AI - Process prediction, new UX
Track
PCB systems design
Shift Left: Find FPGA Bugs Before Simulation and Hardware
Find out how linting, clock-domain crossing checks and automated formal analysis can identify common FPGA design issues before full simulation or hardware testing. This session will demonstrate how early verification can reduce debug effort, avoid costly design iterations and improve design quality.
Track
FPGA verification
03:45 PM
The Intersection of AI & Electronic Systems Design - What's New in Xpedition
As electronic systems reach unprecedented levels of complexity, the traditional methods of design and verification have reached a breaking point. This presentation moves past the theoretical to demonstrate how industrial-grade AI is being deployed today to solve critical bottlenecks in electronic systems design. We will highlight the transition path from manual, heuristic-based processes to AI-orchestrated workflows, where AI agents manage complex, multi-domain design tasks, allowing engineers to reclaim their time for high-level innovation and enabling engineering teams to achieve radical improvements in speed, cost, and first-pass success.
Track
PCB systems design
AI-Assisted FPGA Development and Verification
See how AI-assisted tools can support FPGA engineers with design understanding, code quality, verification and debug. Through practical examples, this session will explore where AI can save engineering time while keeping the engineer in control of the results.
Track
FPGA verification
04:30 PM
Q&A