Logo - Siemens EDA Forum PCB & FPGA Design 2026 - Eindhoven
Servicenavigation
10:45 AM
What's New in Questa One for FPGA Verification
Explore the latest Questa One capabilities for FPGA simulation and debug, including improved VHDL support, faster simulation and advanced debugging. See how these enhancements can help engineering teams find problems earlier and shorten verification cycles.
Track
FPGA verification
01:00 PM
Taking VHDL Verification Beyond Directed Testing
Discover practical ways to move beyond hand-written directed tests using reusable verification components, constrained-random testing and functional coverage. This session will show how VHDL teams can improve test quality and uncover corner-case bugs without having to replace their existing methodology.
Track
FPGA verification
01:45 PM
Bringing FPGA Verification into Continuous Integration
Learn how to integrate FPGA simulation and regression testing into automated development workflows using Git, Jenkins and other continuous integration platforms. See how automation can provide faster feedback, improve repeatability and prevent problems from reaching later stages of development.
Track
FPGA verification
03:00 PM
Shift Left: Find FPGA Bugs Before Simulation and Hardware
Find out how linting, clock-domain crossing checks and automated formal analysis can identify common FPGA design issues before full simulation or hardware testing. This session will demonstrate how early verification can reduce debug effort, avoid costly design iterations and improve design quality.
Track
FPGA verification
03:45 PM
AI-Assisted FPGA Development and Verification
See how AI-assisted tools can support FPGA engineers with design understanding, code quality, verification and debug. Through practical examples, this session will explore where AI can save engineering time while keeping the engineer in control of the results.
Track
FPGA verification