Agenda Siemens EDA Forum Finland

As SoC complexity accelerates and multi-mode, multi-corner (MCMM) operational scenarios proliferate, manual timing constraint development has become one of the largest risks to project schedules. Subtle SDC errors and incorrect timing exceptions often remain hidden until late in physical implementation—or worse, cause silicon failure.

This session introduces Siemens Gencellicon, a unified platform that automates, validates, and manages timing constraints and clock structures from early RTL through physical sign-off. Learn how shifting constraint verification and early chip planning left enables design teams to achieve predictable timing closure, drastically cut costly place-and-route (P&R) iterations, and accelerate time-to-market.

Compelling, to the point, focused on customer value and differentiation Presenter: The AI revolution is driving unprecedented demands for performance, efficiency, and time-to-market. Successful semiconductor teams must manage power continuously across the design cycle while maintaining productivity and design quality. This session highlights how Siemens PowerPro enables a comprehensive RTL low-power methodology through early power estimation, automated optimization, and scalable SoC power exploration. We will also discuss how AI-powered capabilities within the Siemens EDA ecosystem are helping engineers gain deeper insights, automate repetitive tasks, and make more informed power optimization decisions.

For today’s PCB and SoC designers, reliability isn't just about managing temperature—it's about managing the mechanical consequences of heat. From BGA solder fatigue to complex board warpage, the physics of failure are more interconnected than ever.
In this seminar, we demonstrate the latest Siemens workflows for predicting and preventing thermo-mechanical failures before the first prototype is built.
Key Topics:

• Transient Heat Transfer: Moving beyond steady-state to capture real-world thermal solder fatigue.
• Structural Integrity: Integrating random vibration, shock, and drop testing into your design cycle.
• Multi-zone Modeling: How to manage "Unified Detail Levels"—from homogenized board properties to detailed wire-bond analysis—in a single environment.

As modern silicon architectures face increasingly tight power, performance, and area (PPA) constraints, finding the optimal microarchitecture has become the most critical—and time-consuming—phase of hardware design.

Traditional handcrafted RTL forces engineering teams into a costly compromise: because each architectural variant requires weeks or months of manual re-coding, verification, and timing closure, designers typically commit to a single, best-guess microarchitecture early in the cycle. Exploring alternative pipelining depths, memory partitioning schemes, or loop unrolling strategies across multiple target PPA points in RTL is simply impractical under modern tape-out schedules.

High-Level Synthesis (HLS) dismantles this bottleneck by decoupling algorithmic intent from microarchitectural implementation. Using Catapult HLS, designers maintain a single golden source in C++/SystemC and leverage synthesis constraints to rapidly generate, evaluate, and verify dozens of distinct hardware architectures in hours rather than months.

As design complexity and schedule pressures continue to increase, traditional digital implementation flows struggle to deliver optimal power, performance, and area (PPA) within aggressive timelines. In this presentation, we discuss Aprisa AI: how AI in digital implementation helps accelerate design convergence while improving overall PPA, with fully integrated generative AI capabilities and orchestrated AI agents that drastically improve productivity and scale engineering team efforts. The presentation will cover digital implementation technologies from synthesis to place-and-route, and semi-custom low skew routing, while discussing agentic workflows with examples and demos. Join us in this session to learn how to expand your digital implementation workflow and embed AI agents to increase productivity and improve PPA for the next generation of silicon designs