Agenda Siemens EDA Forum Finland

Logo - Siemens EDA Forum FInland 2026 Logo - Siemens EDA Forum FInland 2026
Servicenavigation

 

The agenda below is valid for both events - Tampere, october 27 and Oulu, October 29

11:15 AM

The Rise of the Design and Verification Scientist: Architecting the Future of AI-Driven IC Verification

As semiconductor design complexity outpaces engineering bandwidth, the traditional verification role is transforming from manual execution into high-level strategic direction. This session charts the progression from foundation EDA engines (Questa One) and embedded analytical intelligence to autonomous agentic systems. Attendees will discover how this continuum empowers engineers to operate as design and verification scientists, focusing on architecture and intent while AI orchestrates execution.

Track
SoC and FPGA verification

01:00 PM

Verification IQ: Driving Predictable Closure with Embedded Data Analytics and Machine Learning

Verification IQ establishes a unified data foundation across the verification lifecycle, connecting test planning, regression management, and coverage tracking. This presentation details how embedded intelligence, including Regression Navigator and Coverage Analyzer, eliminates redundant compute cycles and accelerates root-cause identification and coverage closure. Learn how engineering teams leverage data-driven visibility to de-risk delivery schedules, while applications like Testsuite Configurator automate testplan generation and regression setup for VIP protocol compliance.

Track
SoC and FPGA verification

01:45 PM

Shift-Left Bug Hunting: Supercharging Designer Productivity with Interactive AI and Formal Engines

Catching bugs early in the design cycle delivers the highest return on engineering investment and prevents costly downstream escapes. This session explores how Questa Developer and Static Formal Verification (SFV) bring intelligent assistance directly into the engineer's IDE. Attendees will see how automated lint analysis, CDC and RDC autofix, and push-button formal verification eliminate structural flaws and deep logic bugs before design handoff.

Track
SoC and FPGA verification

03:00 PM

Questa One Agentic ToolKit: Accelerating Agentic RTL Sign-Off with Autonomous Flow Agents

Moving beyond conversational assistants, the Questa One Agentic ToolKit introduces autonomous, goal-driven agents that actively orchestrate design and verification workflows. This deep dive demonstrates how the Five Flow Agents, with dedicated focus on Debug and Closure, automate complex root-cause triage, spec hardening, and coverage closure loops. Discover how teams achieve agentic RTL sign-off, reducing multi-week turnaround times to hours.

Track
SoC and FPGA verification

03:45 PM

Session 5 - Track 1

 Coming soon

Track
SoC and FPGA verification