Agenda Siemens EDA Forum Finland

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The agenda below is valid for both events - Tampere, october 27 and Oulu, October 29

11:15 AM

The Rise of the Design and Verification Scientist: Architecting the Future of AI-Driven IC Verification

As semiconductor design complexity outpaces engineering bandwidth, the traditional verification role is transforming from manual execution into high-level strategic direction. This session charts the progression from foundation EDA engines (Questa One) and embedded analytical intelligence to autonomous agentic systems. Attendees will discover how this continuum empowers engineers to operate as design and verification scientists, focusing on architecture and intent while AI orchestrates execution.

Track
SoC and FPGA verification
The Era of the Silicon System: Designing the Future

The shift to software defined Silicon Systems, moving beyond “chip centric” mindset towards convergence of the electronic, mechanical and software domains. Delivering the digital twin of the entire system from concept, design, manufacturing and test.

Track
PCB design & analysis

01:00 PM

Verification IQ: Driving Predictable Closure with Embedded Data Analytics and Machine Learning

Verification IQ establishes a unified data foundation across the verification lifecycle, connecting test planning, regression management, and coverage tracking. This presentation details how embedded intelligence, including Regression Navigator and Coverage Analyzer, eliminates redundant compute cycles and accelerates root-cause identification and coverage closure. Learn how engineering teams leverage data-driven visibility to de-risk delivery schedules, while applications like Testsuite Configurator automate testplan generation and regression setup for VIP protocol compliance.

Track
SoC and FPGA verification
The Intersection of AI & Electronic Systems Design - What's New in Xpedition

As electronic systems reach unprecedented levels of complexity, the traditional methods of design and verification have reached a breaking point. This presentation moves past the theoretical to demonstrate how industrial-grade AI is being deployed today to solve critical bottlenecks in electronic systems design. We will highlight the transition path from manual, heuristic-based processes to AI-orchestrated workflows, where AI agents manage complex, multi-domain design tasks, allowing engineers to reclaim their time for high-level innovation and enabling engineering teams to achieve radical improvements in speed, cost, and first-pass success.

Track
PCB design & analysis

01:45 PM

Shift-Left Bug Hunting: Supercharging Designer Productivity with Interactive AI and Formal Engines

Catching bugs early in the design cycle delivers the highest return on engineering investment and prevents costly downstream escapes. This session explores how Questa Developer and Static Formal Verification (SFV) bring intelligent assistance directly into the engineer's IDE. Attendees will see how automated lint analysis, CDC and RDC autofix, and push-button formal verification eliminate structural flaws and deep logic bugs before design handoff.

Track
SoC and FPGA verification
EDM in the Cloud - What´s New in EDM

Xpedition EDM Cloud Server extends Siemens' proven Enterprise Data Management platform through a Siemens-managed cloud deployment model designed to reduce IT burden, accelerate implementation, and simplify ongoing maintenance. Learn how organizations can improve data governance, collaboration, and design productivity while leveraging enterprise-grade cloud infrastructure and best-practice deployment templates

Track
PCB design & analysis

03:00 PM

Questa One Agentic ToolKit: Accelerating Agentic RTL Sign-Off with Autonomous Flow Agents

Moving beyond conversational assistants, the Questa One Agentic ToolKit introduces autonomous, goal-driven agents that actively orchestrate design and verification workflows. This deep dive demonstrates how the Five Flow Agents, with dedicated focus on Debug and Closure, automate complex root-cause triage, spec hardening, and coverage closure loops. Discover how teams achieve agentic RTL sign-off, reducing multi-week turnaround times to hours.

Track
SoC and FPGA verification
Where Better PCB Design Begins - What´s New in HyperLynx

Front-end design constraint planning is the first step toward analysis-driven PCB design. By shifting constraint definition and validation earlier in the process, teams can improve predictability, catch issues sooner, and avoid costly late-stage iterations. Siemens EDA PCB analysis tools enable this shift-left approach in the front-end phase, helping lay the foundation for more efficient, reliable, and optimized PCB development.

Track
PCB design & analysis

03:45 PM

Session 5 - Track 1

 Coming soon

Track
SoC and FPGA verification
Invent the future, don’t inspect the past

This session starts with an introduction to HyperLynX DRC, covering its role in PCB design verification and how analysis-driven rule checking helps identify design issues early in the development process. Building on this foundation, attendees will learn a practical workflow for creating HyperLynX DRC custom rule checks with AI support. The session demonstrates how complex verification concepts can be transformed into executable checks, enabling faster validation.

Track
PCB design & analysis