Agenda Siemens EDA Forum Finland

As semiconductor design complexity outpaces engineering bandwidth, the traditional verification role is transforming from manual execution into high-level strategic direction. This session charts the progression from foundation EDA engines (Questa One) and embedded analytical intelligence to autonomous agentic systems. Attendees will discover how this continuum empowers engineers to operate as design and verification scientists, focusing on architecture and intent while AI orchestrates execution.

Modern semiconductor technologies like Gate-All-Around (GAA), chiplets, 3D IC and photonics are driving significant complexity in circuit architectures to meet evolving specifications of each chipmaker’s next-gen chip. High-quality verification is necessary across design phases amidst compressing development deadlines. Solido Simulation Suite equips design engineers with state-of-the-art, AI-powered SPICE, FastSPICE and mixed-signal simulators that deliver high performance with reliable quality. Built-in generative and agentic AI capabilities further enhance productivity, enabling engineers to simplify complex tasks through natural language directives. With seamless integrated flows with Calibre, Tessent, Questa and EBS technologies, Solido is an integral part of Siemens EDA solutions for analog, RF, custom digital, memory, library IP, SoC and 3D IC development. Join this session to learn how Solido Simulation Suite tackles today's toughest verification challenges.

As SoC complexity accelerates and multi-mode, multi-corner (MCMM) operational scenarios proliferate, manual timing constraint development has become one of the largest risks to project schedules. Subtle SDC errors and incorrect timing exceptions often remain hidden until late in physical implementation—or worse, cause silicon failure.

This session introduces Siemens Gencellicon, a unified platform that automates, validates, and manages timing constraints and clock structures from early RTL through physical sign-off. Learn how shifting constraint verification and early chip planning left enables design teams to achieve predictable timing closure, drastically cut costly place-and-route (P&R) iterations, and accelerate time-to-market.

Verification IQ establishes a unified data foundation across the verification lifecycle, connecting test planning, regression management, and coverage tracking. This presentation details how embedded intelligence, including Regression Navigator and Coverage Analyzer, eliminates redundant compute cycles and accelerates root-cause identification and coverage closure. Learn how engineering teams leverage data-driven visibility to de-risk delivery schedules, while applications like Testsuite Configurator automate testplan generation and regression setup for VIP protocol compliance.

Modern semiconductor designs demand seamless integration across the full design flow, spanning schematic capture, layout and verification. Traditional, disjointed approaches fall short of the accuracy and efficiency needed as advanced nodes push ever-stricter power, performance, area and yield targets. Solido verification and layout analysis technologies, coupled with schematic and layout design editors, deliver a highly differentiated, unified solution enhanced by a generative and agentic AI layer that empowers engineers through natural language interaction and intelligent automation, accelerating design closure for high-sigma targeted designs. This comprehensive design and verification environment provides a direct focus on deep parasitic analysis, driving an expedited workflow that scales with complex design requirements where traditional, disjointed approaches fall short.

Compelling, to the point, focused on customer value and differentiation Presenter: The AI revolution is driving unprecedented demands for performance, efficiency, and time-to-market. Successful semiconductor teams must manage power continuously across the design cycle while maintaining productivity and design quality. This session highlights how Siemens PowerPro enables a comprehensive RTL low-power methodology through early power estimation, automated optimization, and scalable SoC power exploration. We will also discuss how AI-powered capabilities within the Siemens EDA ecosystem are helping engineers gain deeper insights, automate repetitive tasks, and make more informed power optimization decisions.

Catching bugs early in the design cycle delivers the highest return on engineering investment and prevents costly downstream escapes. This session explores how Questa Developer and Static Formal Verification (SFV) bring intelligent assistance directly into the engineer's IDE. Attendees will see how automated lint analysis, CDC and RDC autofix, and push-button formal verification eliminate structural flaws and deep logic bugs before design handoff.

Library IP quality directly impacts power, performance, and area (PPA) outcomes, design schedule predictability, and silicon success. As SoC complexity grows, teams face pressure to characterize, validate and select IP earlier and more accurately, before costly issues compound downstream. This session presents how the Solido Characterization Suite and Solido IP Validation Suite together enable a shift-left approach across the full IP lifecycle. The recently launched Solido Characterizer delivers up to 5x faster, silicon-accurate Liberty model characterization with AI-powered engines across standard cell, memory, IO and custom analog IP, while Solido Generator automates Liberty model generation. For validation, Solido Crosscheck catches multi-view inconsistencies early and Solido IPdelta enables efficient version-to-version comparison. With Solido Fuse AI, both suites are transitioning to AI-powered flows that surface insights faster and scale across IP types, helping teams deliver integration-ready IP and achieve first-pass silicon success.

For today’s PCB and SoC designers, reliability isn't just about managing temperature—it's about managing the mechanical consequences of heat. From BGA solder fatigue to complex board warpage, the physics of failure are more interconnected than ever.
In this seminar, we demonstrate the latest Siemens workflows for predicting and preventing thermo-mechanical failures before the first prototype is built.
Key Topics:

• Transient Heat Transfer: Moving beyond steady-state to capture real-world thermal solder fatigue.
• Structural Integrity: Integrating random vibration, shock, and drop testing into your design cycle.
• Multi-zone Modeling: How to manage "Unified Detail Levels"—from homogenized board properties to detailed wire-bond analysis—in a single environment.

Moving beyond conversational assistants, the Questa One Agentic ToolKit introduces autonomous, goal-driven agents that actively orchestrate design and verification workflows. This deep dive demonstrates how the Five Flow Agents, with dedicated focus on Debug and Closure, automate complex root-cause triage, spec hardening, and coverage closure loops. Discover how teams achieve agentic RTL sign-off, reducing multi-week turnaround times to hours.

Fuse AI is a Siemens initiative allowing customers to build open, secure, and multimodal internal AI capabilities based on any LLM and any data. Calibre Vision AI allows you to read in huge DRC databases fast and focus on the ones that matter most. Calibre RVE Check Assist allows you to see more debug information for difficult to understand DRC rules, and to build the easy access best practices to fix them. Calibre AI Run Advisor allows you to get guidelines on how to improve the run time. Calibre agentic AI flows allow you to drive and automate your Calibre tasks with a natural language communication.

As modern silicon architectures face increasingly tight power, performance, and area (PPA) constraints, finding the optimal microarchitecture has become the most critical—and time-consuming—phase of hardware design.

Traditional handcrafted RTL forces engineering teams into a costly compromise: because each architectural variant requires weeks or months of manual re-coding, verification, and timing closure, designers typically commit to a single, best-guess microarchitecture early in the cycle. Exploring alternative pipelining depths, memory partitioning schemes, or loop unrolling strategies across multiple target PPA points in RTL is simply impractical under modern tape-out schedules.

High-Level Synthesis (HLS) dismantles this bottleneck by decoupling algorithmic intent from microarchitectural implementation. Using Catapult HLS, designers maintain a single golden source in C++/SystemC and leverage synthesis constraints to rapidly generate, evaluate, and verify dozens of distinct hardware architectures in hours rather than months.

 Coming soon

Dynamic IR drop and electromigration violations are increasingly discovered late in the design cycle, when layout changes are expensive and iterations between layout engineers and circuit designers stretch from days to weeks. This talk presents an integrated flow that closes that loop by feeding mPower EMIR analysis results directly into Calibre DesignEnhancer Power Grid Enhancement (DE PGE), so that fixes are targeted at analyzed hotspots rather than applied blindly across the full chip.

As design complexity and schedule pressures continue to increase, traditional digital implementation flows struggle to deliver optimal power, performance, and area (PPA) within aggressive timelines. In this presentation, we discuss Aprisa AI: how AI in digital implementation helps accelerate design convergence while improving overall PPA, with fully integrated generative AI capabilities and orchestrated AI agents that drastically improve productivity and scale engineering team efforts. The presentation will cover digital implementation technologies from synthesis to place-and-route, and semi-custom low skew routing, while discussing agentic workflows with examples and demos. Join us in this session to learn how to expand your digital implementation workflow and embed AI agents to increase productivity and improve PPA for the next generation of silicon designs