Agenda Siemens EDA Forum Finland

As semiconductor design complexity outpaces engineering bandwidth, the traditional verification role is transforming from manual execution into high-level strategic direction. This session charts the progression from foundation EDA engines (Questa One) and embedded analytical intelligence to autonomous agentic systems. Attendees will discover how this continuum empowers engineers to operate as design and verification scientists, focusing on architecture and intent while AI orchestrates execution.

The shift to software defined Silicon Systems, moving beyond “chip centric” mindset towards convergence of the electronic, mechanical and software domains. Delivering the digital twin of the entire system from concept, design, manufacturing and test.

Modern semiconductor technologies like Gate-All-Around (GAA), chiplets, 3D IC and photonics are driving significant complexity in circuit architectures to meet evolving specifications of each chipmaker’s next-gen chip. High-quality verification is necessary across design phases amidst compressing development deadlines. Solido Simulation Suite equips design engineers with state-of-the-art, AI-powered SPICE, FastSPICE and mixed-signal simulators that deliver high performance with reliable quality. Built-in generative and agentic AI capabilities further enhance productivity, enabling engineers to simplify complex tasks through natural language directives. With seamless integrated flows with Calibre, Tessent, Questa and EBS technologies, Solido is an integral part of Siemens EDA solutions for analog, RF, custom digital, memory, library IP, SoC and 3D IC development. Join this session to learn how Solido Simulation Suite tackles today's toughest verification challenges.

Verification IQ establishes a unified data foundation across the verification lifecycle, connecting test planning, regression management, and coverage tracking. This presentation details how embedded intelligence, including Regression Navigator and Coverage Analyzer, eliminates redundant compute cycles and accelerates root-cause identification and coverage closure. Learn how engineering teams leverage data-driven visibility to de-risk delivery schedules, while applications like Testsuite Configurator automate testplan generation and regression setup for VIP protocol compliance.

As electronic systems reach unprecedented levels of complexity, the traditional methods of design and verification have reached a breaking point. This presentation moves past the theoretical to demonstrate how industrial-grade AI is being deployed today to solve critical bottlenecks in electronic systems design. We will highlight the transition path from manual, heuristic-based processes to AI-orchestrated workflows, where AI agents manage complex, multi-domain design tasks, allowing engineers to reclaim their time for high-level innovation and enabling engineering teams to achieve radical improvements in speed, cost, and first-pass success.

Modern semiconductor designs demand seamless integration across the full design flow, spanning schematic capture, layout and verification. Traditional, disjointed approaches fall short of the accuracy and efficiency needed as advanced nodes push ever-stricter power, performance, area and yield targets. Solido verification and layout analysis technologies, coupled with schematic and layout design editors, deliver a highly differentiated, unified solution enhanced by a generative and agentic AI layer that empowers engineers through natural language interaction and intelligent automation, accelerating design closure for high-sigma targeted designs. This comprehensive design and verification environment provides a direct focus on deep parasitic analysis, driving an expedited workflow that scales with complex design requirements where traditional, disjointed approaches fall short.

Catching bugs early in the design cycle delivers the highest return on engineering investment and prevents costly downstream escapes. This session explores how Questa Developer and Static Formal Verification (SFV) bring intelligent assistance directly into the engineer's IDE. Attendees will see how automated lint analysis, CDC and RDC autofix, and push-button formal verification eliminate structural flaws and deep logic bugs before design handoff.

Xpedition EDM Cloud Server extends Siemens' proven Enterprise Data Management platform through a Siemens-managed cloud deployment model designed to reduce IT burden, accelerate implementation, and simplify ongoing maintenance. Learn how organizations can improve data governance, collaboration, and design productivity while leveraging enterprise-grade cloud infrastructure and best-practice deployment templates

Library IP quality directly impacts power, performance, and area (PPA) outcomes, design schedule predictability, and silicon success. As SoC complexity grows, teams face pressure to characterize, validate and select IP earlier and more accurately, before costly issues compound downstream. This session presents how the Solido Characterization Suite and Solido IP Validation Suite together enable a shift-left approach across the full IP lifecycle. The recently launched Solido Characterizer delivers up to 5x faster, silicon-accurate Liberty model characterization with AI-powered engines across standard cell, memory, IO and custom analog IP, while Solido Generator automates Liberty model generation. For validation, Solido Crosscheck catches multi-view inconsistencies early and Solido IPdelta enables efficient version-to-version comparison. With Solido Fuse AI, both suites are transitioning to AI-powered flows that surface insights faster and scale across IP types, helping teams deliver integration-ready IP and achieve first-pass silicon success.

Moving beyond conversational assistants, the Questa One Agentic ToolKit introduces autonomous, goal-driven agents that actively orchestrate design and verification workflows. This deep dive demonstrates how the Five Flow Agents, with dedicated focus on Debug and Closure, automate complex root-cause triage, spec hardening, and coverage closure loops. Discover how teams achieve agentic RTL sign-off, reducing multi-week turnaround times to hours.

Front-end design constraint planning is the first step toward analysis-driven PCB design. By shifting constraint definition and validation earlier in the process, teams can improve predictability, catch issues sooner, and avoid costly late-stage iterations. Siemens EDA PCB analysis tools enable this shift-left approach in the front-end phase, helping lay the foundation for more efficient, reliable, and optimized PCB development.

Fuse AI is a Siemens initiative allowing customers to build open, secure, and multimodal internal AI capabilities based on any LLM and any data. Calibre Vision AI allows you to read in huge DRC databases fast and focus on the ones that matter most. Calibre RVE Check Assist allows you to see more debug information for difficult to understand DRC rules, and to build the easy access best practices to fix them. Calibre AI Run Advisor allows you to get guidelines on how to improve the run time. Calibre agentic AI flows allow you to drive and automate your Calibre tasks with a natural language communication.

 Coming soon

This session starts with an introduction to HyperLynX DRC, covering its role in PCB design verification and how analysis-driven rule checking helps identify design issues early in the development process. Building on this foundation, attendees will learn a practical workflow for creating HyperLynX DRC custom rule checks with AI support. The session demonstrates how complex verification concepts can be transformed into executable checks, enabling faster validation.

Dynamic IR drop and electromigration violations are increasingly discovered late in the design cycle, when layout changes are expensive and iterations between layout engineers and circuit designers stretch from days to weeks. This talk presents an integrated flow that closes that loop by feeding mPower EMIR analysis results directly into Calibre DesignEnhancer Power Grid Enhancement (DE PGE), so that fixes are targeted at analyzed hotspots rather than applied blindly across the full chip.